XNetSim is a simulator for electronic circuits at Register Transfer Level (RTL) consisting of Xilinx primitives. It is used for debugging of HDL designs written in VHDL or Veriog targeted at Xilinx FPGAs. In contrast to HDL simulators like GHDL or Icarus verilog it does not include a HDL parser but instead relies on Xilinx utilities (namely xst and ngc2edif).
XNetSim only supports netlists which solely consist of Xilinx primitives as are used for Xilinx FPGAs. This way XNetSim simulation is very close to what actually happens in hardware and is well suited for debugging FPGAs. Currently there is support for all major Xilinx primitives used in Spartan-3E series including RAMBs and distributed rams except asynchronous latches and asynchronous feedback (i.e. cyclic graphs).
From a black box point of view XNetSim turns netlists in a specific file format (SNF) into cpp files which can in turn be compiled with a C++ compiler.
SNF files are basically EDIF netlists with less syntax overhead. They can be obtained by means of a edif_extract (part of this package), which was written in Java in order to utilize a third party library for parsing EDIF files called BYU EDIF Tools. EDIF files containing Xilinx primitives are written by ngc2edif (a Xilinx utility). ngc2edif takes NGC files that are the output of xst (the Xilinx HDL synthesizer).
Testbenches are written in C++ and linked with object files from XNetSim.
A more complete manual can be downloaded below.